A2dp

The following information is from /etc/audio/media_a2dp.txt. The registers have been matched to descriptions taken from a Texas Instruments TPS65930/TPS65920 OMAP Power Management Chip datasheet.

<source lang="text"> begin media_a2dp

   setreg 0x02 0xc1 // **OPTION REGISTER**; Audio/voice digital filter power control Two interpretations of the option register, depending on whether option 1 or option 2 is enabled (CODEC_MODE register, OPT_MODE bit)
   setreg 0x04 0x01 // **MICBIAS_CTL REGISTER**; Microphone bias and analog microphone amplifier power control register. If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting.
   setreg 0x05 0x11 // **ANAMICL REGISTER**; Analog microphone left control and offset cancellation control register Analog microphone left: Main microphone, headset microphone, carkit microphone, or auxiliary left microphone can be routed to the input of the A/D converters separately (only one enable bit at 1). If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting.
   setreg 0x06 0x00 // **ANAMICR REGISTER**; Analog microphone right control register Analog microphone right: Submicrophone or auxiliary right microphone can be routed to the input of the A/D converters separately (only one enable bit at 1). If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting
   setreg 0x07 0x08 // **AVADC_CTL REGISTER**; Audio/voice ADC control register If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting.
   setreg 0x08 0x00 // **ADCMICSEL REGISTER**; Digital audio/voice TX filter input select

1. ATXL1=0dB

   setreg 0x0a 0x00 // **ATXL1PGA REGISTER**; Audio TXL1 gain control register
   setreg 0x0e 0x01 // **AUDIO_IF REGISTER**; Control mode for audio interface If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting.
   setreg 0x0f 0x00 // **VOICE_IF REGISTER**; Control mode for voice interface If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting.

1. 0dB

   setreg 0x10 0x3f // **ARXR1PGA REGISTER**; Audio RXR1 gain control register
   setreg 0x17 0x01 // **AVDAC_CTL REGISTER**; Power control register for audio DAC and voice DAC If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ is powered off, the digital filter, analog section, and Bluetooth/voice/ audio interfaces are switched off, regardless of this register setting.

1. 0dB

   setreg 0x1a 0x33 // **ARXR1_APGA_CTL REGISTER**; Audio RXR1 analog PGA control register. If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ is powered off, the digital filter, analog section, and Bluetooth/voice/ audio interfaces areswitched off, regardless of this register setting.
   setreg 0x1e 0x00 // **BT_IF REGISTER**; Control mode for Bluetooth interface Note: The data format of the Bluetooth interface is defined by voice interface (VOICE_IF register at address0x0F, VIF_FORMAT bit, see Table 13-20). If the codec powers control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting.
   setreg 0x21 0x00 // **EAR_CTL REGISTER**; Earphone amplifier control register Voice A ®IN1, Audio L1 ® IN2, Audio L2 ® IN3, Audio R1 ® IN4 If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting. Earphone output (EAR): Voice, audio L1, audio L2, or audio R1 can be routed to the output separately (only one enable bit at 1); or voice can be mixed with audio R1, audio L1, or audio L2 and routed to the output (EAR_VOICE_EN = 1, EAR_AR1_EN = 1, EAR_AL1_EN = 1, or EAR_AL2_EN = 1).
   setreg 0x25 0x00 // **PREDL_CTL REGISTER**; Predriver class D left amplifier control register Voice A –> IN1, Audio L1 –> IN2, Audio L2 –> IN3, Audio R2 –> IN4If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting. Predriver class D output left (PREDL): Voice, audio L1, audio L2, or audio R2 can be routed to the output separately (only one enable bit at 1); or voice can be mixed with audio L1, audio L2, or audio R2 and routed to the output (PREDL_VOICE_EN = 1, PREDL_AL1_EN = 1, PREDL_AL2_EN = 1, or PREDL_AR2_EN = 1, respectively).
   setreg 0x26 0x00 // **PREDR_CTL REGISTER**; Predriver class D left amplifier control register Voice A –> IN1, Audio R1 –> IN2, Audio R2 –> IN3, Audio L2 –> IN4 If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumedvalid. If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/voice/audio interfaces are switched off, regardless of this register setting. Predriver class D output right (PREDR): Voice, audio R1, audio R2, or audio L2 can be routed to the output separately (only one enable bit at 1); or voice can be mixed with audio R1, audio R2, or audio L2 and routed to the output (PREDR_VOICE_EN = 1, PREDR_AR1_EN = 1, PREDR_AR2_EN = 1, or PREDR_AL2_EN = 1).
   setreg 0x2a 0x20 // **HFR_CTL REGISTER**; Hands-free right class D amplifier control register. If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid.If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting. The class D amplifier is in application mode if all EN bits are in high state.
   setreg 0x2a 0x30 // **HFR_CTL REGISTER**; Hands-free right class D amplifier control register. If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid.If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting. The class D amplifier is in application mode if all EN bits are in high state.
   setreg 0x2a 0x3d // **HFR_CTL REGISTER**; Hands-free right class D amplifier control register. If the codec power control register bit (CODECPDZ) setting is powered on, this register setting is assumed valid.If the CODECPDZ setting is powered off, the digital filter, analog section, and Bluetooth/ voice/audio interfaces are switched off, regardless of this register setting. The class D amplifier is in application mode if all EN bits are in high state.
   setreg 0x3f 0x00 // **PCMBTMUX REGISTER**; PCM/BT mux and tone adder control register
   setreg 0x43 0x03 // **RX_PATH_SEL REGISTER**; RX path select control register

1. ANAMIC_GAIN=+12dB

   setreg 0x48 0x02 // **ANAMIC_GAIN REGISTER**; Gain control of the microphone amplifier

end

begin media_a2dp_media end

begin media_a2dp_default end

begin media_a2dp_powerdown end

begin media_a2dp_powerup end </source>